The trend in high performance computers is to use increasing number of processors operating cooperatively in common memory. The memory is broken into a number of independently addressable modules known as Basic Storage Modules (BSM). If there are `n` processors, the number of Basic Storage Modules `m` is likely to be greater than `n`. Since the processors require equal access to the memories, there is some form of `n.times.m` switch to select the appropriate path between the processor and the currently addressed memory for storing and retrieval of the data.
Parameters of importance to the performance of the system are processor cycle time, bandwidth, electrical path length, round trip delay, and timing skew.
The processor cycle time is minimized by placing the cycle determining path elements in the closest possible proximity to each other. The bandwidth between processor and memory is achieved by using the fastest possible data rate over a large number of parallel connections between the processors and switches, and the switches and the Basic Storage Modules. The electrical path length is the length between data latching points on different, but interconnected functional units as measured in nanoseconds. The total round trip delay from a processor to a memory and back is known as the memory latency. This includes a number of electrical path lengths. The skew is the electrical path length differences due to variations in routing from one point to another. The area of memory is determined by the surface area required to contain the storage chips and the logic support chips. In a typical case of a Card-on-Board (COB) memory, all of the external interconnections are placed on one edge of the card. When the memory is accessed for data, a signal must travel from the input edge of the card to the far side, and return back to the original edge. In so doing, it has traversed the width of the card twice, with attendant delay, and the required data appears at the same edge from which it was requested, and therefore no closer to the final destination.
It is evident that with these conventional systems, there is significant skew or differences in electrical path due to accessing different parts of the memory or different memory chips in different sections of the memory, or from different processors.